\doxysection{LTDC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_l_t_d_c___type_def}{}\label{struct_l_t_d_c___type_def}\index{LTDC\_TypeDef@{LTDC\_TypeDef}}


LCD-\/\+TFT Display Controller.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a1a43b1a297bbe2126e6697a09d21612d}{RESERVED0}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_aa5bb98a48470eaf50559e916bce23278}{SSCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_aefc3daf9db06d441115572be02bb49bd}{BPCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a20602a2e34b3e4e97e07474e5ad9c22b}{AWCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a7a7b8762321bdcdc8def7a6ace94a455}{TWCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a154e0514cfca7449156dd5a9133631ac}{GCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_aadd4b8262474fe610f5414e1ff2fbcbe}{RESERVED1}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a502dd9d2d17025a90bdf968eb29827f2}{SRCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_ae3e85d4ed370a42e7fd46d059dffaaa8}{RESERVED2}} \mbox{[}1\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_acf20a59c07d3e013d0207b1719b973b6}{BCCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_afffbe3c266a4f2bd842eb96103b65dac}{RESERVED3}} \mbox{[}1\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a0ab6c92574cc246707aa1371e3c5cb85}{IER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a2e3f3fba908b85d2fcf1eaab6b5600bf}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a7c7225eb9029a81f17b60cf4104eaffb}{ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a74a5f74bb4f174bbda1e2dc3cce9f536}{LIPCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_af019d85ce2b876ee99d994a09de12ec3}{CPSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___type_def_a6d6675f23322e241122468935ee60ed1}{CDSR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
LCD-\/\+TFT Display Controller. 

\label{doc-variable-members}
\Hypertarget{struct_l_t_d_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_l_t_d_c___type_def_a20602a2e34b3e4e97e07474e5ad9c22b}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!AWCR@{AWCR}}
\index{AWCR@{AWCR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AWCR}{AWCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a20602a2e34b3e4e97e07474e5ad9c22b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+AWCR}

LTDC Active Width Configuration Register, Address offset\+: 0x10 \Hypertarget{struct_l_t_d_c___type_def_acf20a59c07d3e013d0207b1719b973b6}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!BCCR@{BCCR}}
\index{BCCR@{BCCR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BCCR}{BCCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_acf20a59c07d3e013d0207b1719b973b6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+BCCR}

LTDC Background Color Configuration Register, Address offset\+: 0x2C \Hypertarget{struct_l_t_d_c___type_def_aefc3daf9db06d441115572be02bb49bd}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!BPCR@{BPCR}}
\index{BPCR@{BPCR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BPCR}{BPCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_aefc3daf9db06d441115572be02bb49bd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+BPCR}

LTDC Back Porch Configuration Register, Address offset\+: 0x0C \Hypertarget{struct_l_t_d_c___type_def_a6d6675f23322e241122468935ee60ed1}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!CDSR@{CDSR}}
\index{CDSR@{CDSR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CDSR}{CDSR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a6d6675f23322e241122468935ee60ed1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+CDSR}

LTDC Current Display Status Register, Address offset\+: 0x48 \Hypertarget{struct_l_t_d_c___type_def_af019d85ce2b876ee99d994a09de12ec3}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!CPSR@{CPSR}}
\index{CPSR@{CPSR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CPSR}{CPSR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_af019d85ce2b876ee99d994a09de12ec3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+CPSR}

LTDC Current Position Status Register, Address offset\+: 0x44 \Hypertarget{struct_l_t_d_c___type_def_a154e0514cfca7449156dd5a9133631ac}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!GCR@{GCR}}
\index{GCR@{GCR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{GCR}{GCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a154e0514cfca7449156dd5a9133631ac} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+GCR}

LTDC Global Control Register, Address offset\+: 0x18 \Hypertarget{struct_l_t_d_c___type_def_a7c7225eb9029a81f17b60cf4104eaffb}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a7c7225eb9029a81f17b60cf4104eaffb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+ICR}

LTDC Interrupt Clear Register, Address offset\+: 0x3C \Hypertarget{struct_l_t_d_c___type_def_a0ab6c92574cc246707aa1371e3c5cb85}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!IER@{IER}}
\index{IER@{IER}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IER}{IER}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a0ab6c92574cc246707aa1371e3c5cb85} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+IER}

LTDC Interrupt Enable Register, Address offset\+: 0x34 \Hypertarget{struct_l_t_d_c___type_def_a2e3f3fba908b85d2fcf1eaab6b5600bf}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a2e3f3fba908b85d2fcf1eaab6b5600bf} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+ISR}

LTDC Interrupt Status Register, Address offset\+: 0x38 \Hypertarget{struct_l_t_d_c___type_def_a74a5f74bb4f174bbda1e2dc3cce9f536}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!LIPCR@{LIPCR}}
\index{LIPCR@{LIPCR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LIPCR}{LIPCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a74a5f74bb4f174bbda1e2dc3cce9f536} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+LIPCR}

LTDC Line Interrupt Position Configuration Register, Address offset\+: 0x40 \Hypertarget{struct_l_t_d_c___type_def_a1a43b1a297bbe2126e6697a09d21612d}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a1a43b1a297bbe2126e6697a09d21612d} 
uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+RESERVED0\mbox{[}2\mbox{]}}

Reserved, 0x00-\/0x04 \Hypertarget{struct_l_t_d_c___type_def_aadd4b8262474fe610f5414e1ff2fbcbe}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_aadd4b8262474fe610f5414e1ff2fbcbe} 
uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+RESERVED1\mbox{[}2\mbox{]}}

Reserved, 0x1\+C-\/0x20 \Hypertarget{struct_l_t_d_c___type_def_ae3e85d4ed370a42e7fd46d059dffaaa8}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_ae3e85d4ed370a42e7fd46d059dffaaa8} 
uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+RESERVED2\mbox{[}1\mbox{]}}

Reserved, 0x28 \Hypertarget{struct_l_t_d_c___type_def_afffbe3c266a4f2bd842eb96103b65dac}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!RESERVED3@{RESERVED3}}
\index{RESERVED3@{RESERVED3}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED3}{RESERVED3}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_afffbe3c266a4f2bd842eb96103b65dac} 
uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+RESERVED3\mbox{[}1\mbox{]}}

Reserved, 0x30 \Hypertarget{struct_l_t_d_c___type_def_a502dd9d2d17025a90bdf968eb29827f2}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!SRCR@{SRCR}}
\index{SRCR@{SRCR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SRCR}{SRCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a502dd9d2d17025a90bdf968eb29827f2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+SRCR}

LTDC Shadow Reload Configuration Register, Address offset\+: 0x24 \Hypertarget{struct_l_t_d_c___type_def_aa5bb98a48470eaf50559e916bce23278}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!SSCR@{SSCR}}
\index{SSCR@{SSCR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SSCR}{SSCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_aa5bb98a48470eaf50559e916bce23278} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+SSCR}

LTDC Synchronization Size Configuration Register, Address offset\+: 0x08 \Hypertarget{struct_l_t_d_c___type_def_a7a7b8762321bdcdc8def7a6ace94a455}\index{LTDC\_TypeDef@{LTDC\_TypeDef}!TWCR@{TWCR}}
\index{TWCR@{TWCR}!LTDC\_TypeDef@{LTDC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TWCR}{TWCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___type_def_a7a7b8762321bdcdc8def7a6ace94a455} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Type\+Def\+::\+TWCR}

LTDC Total Width Configuration Register, Address offset\+: 0x14 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
